VLSI IEEE Project titles 2020

VLSI 2019 IEEE Project Titles

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  1. A Robust Energy/Area-Efficient Forwarded-ClockReceiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
  2. Full-Swing Local Bitline SRAM ArchitectureBased on the 22-nm FinFET Technology for Low-Voltage Operation
  3. Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
  4. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
  5. The Serial Commutator (SC) FFT
  6. An Improved Signed Digit Representation Approach for Constant Vector Multiplication
  7. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
  8. A New XOR-Free Approach for Implementation of Convolutional Encoder
  9. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
  10. Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation
  11. Implementation of a PID control PWM Module on FPGA
  12. Built-in Self Testing of FPGAs
  13. An FPGA-Based Cloud System for Massive ECG Data Analysis
  14. Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip
  15. VLSI Implementation of Fully Parallel LTE Turbo Decoders
  16. A High Throughput List Decoder Architecture For Polar Codes
  17. High-Performance NB-LDPC Decoder With Reduction of Message Exchange
  18. A High-Speed FPGA Implementationof an RSD-Based ECC Processor
  19. Low-Power ECG-Based Processor forPredicting Ventricular Arrhythmia
  20. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
  21. Configurable Parallel Hardware Architecture forEfficient Integral Histogram Image Computing
  22. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
  23. A Normal I/O Order Radix-2 FFT Architecture to ProcessTwin Data Streams for MIMO
  24. Unequal-Error-Protection Error Correction Codes for theEmbedded Memories in Digital Signal Processors
  25. Hybrid LUT/Multiplexer FPGA Logic Architectures
  26. A Dynamically Reconfigurable Multi-ASIP Architecture forMultistandard and Multimode Turbo Decoding
  27. Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
  28. A Fully Digital Front-End Architecture for ECGAcquisition System With 0.5 V Supply
  29. A Low-cost and Modular Receiver for MIMO SDR
  30. High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
  31. Frequency-Boost Jitter Reduction forVoltage-Controlled Ring Oscillators
  32. Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
  33. Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
  34. A Low-Power Robust Easily CascadedPentaMTJ-Based Combinational and Sequential Circuits
  35. A 0.1–3.5-GHz Duty-Cycle Measurement andCorrection Technique in 130-nm CMOS
  36. Full-Swing Local Bitline SRAM ArchitectureBased on the 22-nm FinFET Technology for Low-Voltage Operation
  37. A Modified Partial Product Generator for Redundant Binary Multipliers
  38. An Efficient Hardware Implementation of Canny Edge Detection Algorithm
  39. Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation

IEEE 2018 Base Paper

  1. FP – VLSI Implementation of an adaptive Edge Enhanced color interpolation Processor for Real-Time Video Applications
  2. FP -Demonstrating HW-SW Transient Error Mitigation on the single-chip cloud computer data plane
  3. FP -Enhanced Memory reliability against multiple cell upsets using Decimal Matrix code
  4. FP -Wear out Resilience in NOCs through an Aging Aware Adaptive Routing Algorithm
  5. FP -High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications On-Chip Memory Hierarchy in one Coarse-Grained Reconfigurable Architecture to compress memory space and to reduce time
  6. FP -A Voltage based Leakage current calculation scheme and its application to Nanoscale and FinFET Standard cell designs
  7. FP -High Throughput and Low complexity BCH decoding Architecture for Solid-State Drives
  8. FP -Nonbinary LDPC Decoder based on Simplified Enhanced Generalized Bit-Flipping Algorithm
  9. FP -A 2-D Interpolation based ORD Processor with Partial Layer Mapping for MIMO-OFDM Systems
  10. FP -Digitally controlled Pulse Width Modulator for On-Chip Power Management
  11. FP -UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors
  12. FP -High-Throughput Multistandard Transform Core supporting MPEG/H.264/VC-1 using Common Shared Distributed Arithmetic
  13. FP -Alogirthm and Architecture for a Low-Power Content Addressable Memory based on Sparse Clustered Networks
  14. FP -A Variation-Aware Preferential Design approach for Memory- Based Reconfigurable Computing
  15. FP -Asynchronous Domino Logic Pipeline Design Based on Constructed Critical data path
  16. FP -Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
  17. Application Mapping Onto Mesh-Based Network-On-Chip using Discrete Particle Swarm Optimization
  18. FP -Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
  19. FP -Single-Bit Pseudo Parallel Processing Low-oversampling Delta-Sigma Modulator suitable for SDR Wireless Transmitters
  20. FP -A Lattice Reduction Aided MIMO Channel Equalizer in 90 nm CMOS achieving 720 Mb/s
  21. FP -Low Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers
  22. FP -Low-Energy Two-stage Algorithm for High Efficiency Epileptic Seizure Detection
  23. FP -An Ultralow Power Multirate FSK Demodulator for High-Speed Biomedical Zero-IF Receivers
  24. FP -Ultra-High Throughput Low-Power Packet Classification
  25. FP -Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SOC’s
  26. FP -Area-Delay-Power Efficient Fixed-point LMS Adaptive filter with low adaptation delay
  27. FP -Energy Efficiency Optimization through codesign of the Transmitter and Receiver in High-speed On-Chip Interconnects
  28. FP -A Fast application based supply voltage optimization method for dual voltage FPGA
  29. FP -Reliable Low-Power Multiplier Design using Fixed-Width Replica Redundancy block
  30. FP -Low-Power Pulse-Triggered Flip-Flop Design based on a signal feed-through