IEEE Ns2, Ns3 2018 2019 projects
IEEE NS2 PROJECT LIST 2019-2020:
- Dynamic Connectivity Establishment and Cooperative Scheduling for QoS-Aware Wireless Body Area Networks
- On Modeling Shortest Path Length Distribution in Scale-Free Network Topologies
- Real-Time Intersection-based Segment Aware Routing Algorithm for Urban Vehicular Networks
- Traffic-Aware Efficient Mapping of Wireless Body Area Networks to Health Cloud Service Providers in Critical Emergency Situations
- A Realistic Distributed Conditional Privacy Preserving Authentication Scheme for Vehicular Ad Hoc Networks
- Dense-Device-Enabled Cooperative Networks for Efficient and Secure Transmission
- MobiT Distributed and Congestion Resilient Trajectory Based Routing for Vehicular Delay Tolerant Networks
- An Efficient Message-Authentication Scheme Based on Edge Computing for Vehicular Ad Hoc Networks
- CISRP connectivity-aware intersection-based shortest path routing protocol for VANETs in urban environments
- Discovery of Critical Nodes in Road Networks Through Mining From Vehicle Trajectories
- Energy Efficiency and Delay in 5G Ultra Reliable Low Latency Communications System Architectures
- k Nearest Neighbor Search for Location Dependent Sensor Data in MANETs
- Node-Based Distributed Channel Access With Enhanced Delay Characteristics
- LBP: Robust Rate Adaptation Algorithm for SVC Video Streaming
- Heavy-Traffic Analysis of QoE Optimality for On-Demand Video Streams Over Fading Channels
IEEE NS3 PROJECT LIST 2018-2019:
1.A Survey and Performance Evaluation of Ad-Hoc Multi-Hop Routing Protocols for Static Outdoor Networks
2.FACT Fine-Grained Adaptation of Carrier Sense Threshold in IEEE 802.11 WLANs
3.Performance Evaluation of Caching Policies in NDN – an ICN Architecture
4.ROSE Robustness Strategy for Scale-Free Wireless Sensor Networks
5.Simulation Based Performance Evaluation of TCP Variants along with UDP Flow
6.Simulation Model and Comparison for Satellite Links in Ku and Ka Bands for Standards-based on DVB-S2 and NS3
7.A Real-time Aware Routing Strategy in Smart City Environments
8.Multipoint Relay Selection through Estimated Spatial Relation in Smart City Environments
9. D-TCP: Dynamic TCP Congestion Control Algorithm for Next Generation Mobile Networks
10.Detection of Selfish Attack over Wireless Body Area Networks
Low power
1. Ns2-Energy efficient reduce and rank using input adaptive approximations
2. Ns2-Enfire: a spatio-temporal fine-grained reconfigurable hardware
3. Ns2 – Sign-magnitude encoding for efficient vlsi realization of decimal multiplication
4. Ns2 -Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication
5. Ns2 -Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable multipliers
6. Ns2 A way-filtering-based dynamic logical-associative cache architecture for low-energy consumption
7. Ns2- Resource-efficient sram-based ternary content addressable memory
8. Ns2 -A high-efficiency 6.78-mhz full active rectifier with adaptive time delay control for wireless power transmission
High speed data transmission
1. Ns2 -High-speed and low-latency ecc processor implementation over gf(2m) on fpga
2. Ns2 -A 2.5-ps bin size and 6.7-ps resolution fpga time-to-digital converter based on delay wrapping and averaging
3. Ns2 -Comedi: combinatorial election of diagnostic vectors from detection test sets for logic circuits
4. Ns2 – Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding
5. Ns2 -A 2.4-3.6-ghz wideband sub-harmonically injection-locked pll with adaptive injection timing alignment technique
6. Ns2 – Fast automatic frequency calibrator using an adaptive frequency search algorithm
7. Ns2 -A 65-nm cmos constant current source with reduced pvt variation
8. Ns2 – High-speed parallel lfsr architectures based on improved state-space transformations
9. Ns2 – Scalable approach for power droop reduction during scan-based logic bist
10. Ns2 – Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations
11. Ns2 -Stochastic implementation and analysis of dynamical systems similar to the logistic map
Area efficient/ timing & delay reduction
1. Ns2 – Roba multiplier: a rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing
2. Ns2 – Vlsi design of 64bit * 64bit high performance multiplier with redundant binary encoding
3. Ns2 – A method to design single error correction codes with fast decoding for a subset of critical bits
4. Ns2 -Hybrid hardware/software floating-point implementations for optimized area and throughput tradeoffs
5. Ns2 -Efficient soft cancelation decoder architectures for polar codes
6. Ns2 -Low-complexity digit-serial multiplier over gf(2m) based on efficient toeplitz block toeplitz matrix-vector product decomposition
7. Ns2- Efficient designs of multiported memory on fpga
8. Ns2 -Hybrid lut multiplexer fpga logic architectures
9. Ns2 -Fpga realization of low register systolic all-one-polynomial multipliers over gf (2m) and their applications in trinomial multipliers
10. Ns2- Coordinate rotation-based low complexity k-means clustering architecture
11. Ns2 – Coordinate rotation-based low complexity k-means clustering architecture
12. Ns2 -Energy-efficient vlsi realization of binary64 division with redundant number systems
13. Ns2- Hardware-efficient built-in redundancy analysis for memory with various spares
14. Ns2- Reordering tests for efficient fail data collection and tester time reduction
15. Ns2 -An fpga-based hardware accelerator for traffic sign detection
16. Ns2 – Antiwear leveling design for ssds with hybrid ecc capability
17. Ns2 – A fault tolerance technique for combinational circuits based on selective-transistor redundancy
Audio, image & video processing
1. Ns2- A dual-clock vlsi design of h.265 sample adaptive offset estimation for 8k ultra-hd tv encoding
Verification
1. Ns2 – Publicly verifiable watermarking for intellectual property protection in fpga design
2. Ns2 – Interconnection allocation between functional units and registers in high-level synthesis
Networking on chip (noc)
1. Ns2 – Multicast-aware high-performance wireless network-on-chip architectures
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